1. Field of the Invention
This invention relates generally to semiconductor structures and more particularly to a method and structure having an integrated void fill for through silicon via (hereinafter TSV).
2. Description of the Related Art
The designers of electronic equipment are driven to increase the capacity and, generally, the performance that can be extracted per unit volume. This drive has encouraged the adoption of technologies such as stacked packaging in which two or more chips (ICs) are stacked one on top of another in each package, i.e., vertically stacked, with the face of one chip overlying the face of another chip.
One way of fabricating stacked packages is by wafer-level processing, in which two or more wafers are stacked in this manner, with each wafer having metal joining pads on at least one face of the wafer and the joining pads of one wafer confronting the joining pads of the adjacent stacked wafer. Through silicon vias (TSVs) provide one form of electrical interconnection in stacked packages. TSVs can be formed to extend through the stacked wafers at locations spaced from the joining pads to provide wafer-to-wafer electrical interconnections between semiconductor devices of each wafer. The stacked wafers then are joined with packaging elements, e.g., a carrier or package substrate and then are severed into individual packages each containing a plurality of vertically stacked chips.
Once concern of such process of forming stacked packages is that gaps can remain as open paths between the metal joining pads and the TSVs in the interfacial regions between the faces of adjacent chips in each stacked package. The gaps can increase the possibility of electromigration and various other effects that may impact long-term reliability and failure rates of the stacked package.
It would be desirable to provide a method and structure which addresses the above-discussed concerns about the gaps.